Full Chip Thermal Simulation

A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured to the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal di usion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Di erent thermal conductivity can be speci ed for each material layer. The e ect of package on chip temperature distribution is modeled using thermally resistive layers as boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation will be described. The code is applied to the analysis of a realistic design of CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of simulation results will be presented.